1. Field of the Invention
The invention relates to fabrication of integrated circuit devices incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers are used to create a “shadow effect”, which limits the nitrogen dose close to the edges of the active area. This reduction of nitrogen dose leads to an increased gate oxide thickness at the active area adjacent to the shallow trench and increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.
2. Description of the Related Art
In the arrangement of DRAM cell processing using a shallow trench isolation region to realize a small-size capacitor, gate oxide reliability of support oxides is limited by the thickness of the gate oxide at the AA (active area) corners. Therefore, careful optimization of the AA oxidation, (sacrificial) oxide, and gate oxidation is necessary to create the required AA corner rounding and the oxide thickness at the AA corner. In fact, in all too many instances, the oxide is thinner at the corners than at the AA area.
U.S. Pat. No. 5,330,920 discloses a method of controlling gate oxide thickness in the fabrication of semiconductor devices. The process comprises:                forming a sacrificial gate oxide layer on select locations of a semiconductor substrate surface;        implanting nitrogen ions into the select locations of the substrate through the sacrificial gate oxide layer;        thermally annealing the substrate and sacrificial gate oxide layer to assist pile-up of he nitrogen ions at the semiconductor substrate surface;        removing the sacrificial gate oxide layer; and        thermally forming a gate oxide layer on the silicon semiconductor substrate surface, wherein the select locations having nitrogen ion implanted will have a thinner gate oxide layer than a non-implanted region.        
Fabrication of an integrated device using nitrogen implantation is disclosed in U.S. Pat. No. 6,037,639. The process comprises:                providing a channel region defined by a source and drain region of a semiconductor substrate having a gate structure comprising an isolating oxide layer positioned on the channel region and the polysilicon layer positioned on the oxide layer. More specifically, the process comprises forming the nitrogen implanted regions over the semiconductor substrate by implanting nitrogen atoms into those regions and growing spacers from exposed portions of the polysilicon layer. During the spacer growth, the spacer grows vertically as well as laterally extending under the polysilicon edges. Diffusion of nitrogen atoms to the substrate surface forms silicon nitride under the gate edges, which minimizes current leakages into the gate polysilicon.        
U.S. Pat. No. 5,920,779 disclose a process for differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits comprising:                providing a semiconductor substrate having a surface, the semiconductor substrate comprising a first region on which a plurality of first MOS devices are to be formed and a second region on which a plurality of second MOS devices are to be formed;        masking the second region and providing a first concentration of a first dopant in the semiconductor substrate at the surface of the first region without doping the second region;        removing the mask over the second region;        masking the first region and providing a second concentration of a second dopant in the semiconductor substrate at the surface of the second region without doping the first region, wherein the second concentration is different than the first concentration;        oxidizing the surface of the semiconductor substrate to grow a first thickness of oxide on the first region of the semiconductor substrate and to grow a second, different thickness of oxide on the second region in a single oxidizing process; and        forming first MOS devices on the first regions of the semiconductor substrate incorporating the first thickness of oxide and forming second MOS devices on the second region incorporating the second thickness of oxide;        wherein the first and second dopants are both nitrogen and the first concentration is greater than the second concentration.        
In general, a typical way to achieve two oxide thicknesses in one oxidation step is to make use of local nitrogen implantation to reduce the oxidation rate at the implanted sites.
The use of local nitrogen implementation to achieve two oxidation thicknesses in one oxidation step consist of utilizing the process integration scheme of:                growing of the sacrificial oxide;        implantation of dopants through the sacrificial oxide;        employing a photoresist mask to pattern an integrated circuit that includes the first transistor having a first dielectric thickness and a second transistor having a second dielectric thickness;        implanting nitrogen ions to create dual gate oxide devices;        stripping off the photoresist mask and the sacrificial oxide; and        subjecting the gate to oxidation.        
Due to the fact that, in many cases, the gate oxide reliability of support oxide is limited by the thickness of the gate oxide at the AA (active area) corners, and careful optimization of AA oxidation, sac oxide, and gate oxidation is necessary to create the required AA corner rounding and the oxide thickness at the AA corner, there is a need to limit the dual gate nitrogen dose in the AA to the inner part of the gate area to provide increased gate oxide thickness at the active area corner and thereby increase the threshold of the parasitic corner device, reduce sub Vt (threshold voltage) and junction leakage.